1. Field of the Invention
The present invention pertains to a novel high-performance thin film transistor having an active region and a gate, whose active region comprises a poly-Si1-xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1-xGex alloy material and the gate and a method for fabricating such a high-performance thin film transistor.
2. Discussion of the Background
Conventional thin-film transistors (TFTs) are commonly employed in high-density static random access memory cells (SRAMs) for load pull-up devices, as well as used both as switching elements and as peripheral driver circuitry in large-area active-matrix liquid crystal displays (LCDs). In such conventional thin film transistors, polycrystalline silicon (poly-Si) is widely used as the active region. Unfortunately, the performance of a poly-Si TFT degrades substantially as the processing temperature decreases. This performance degradation removes many of the incentives to use a poly-Si TFT, because low-temperature processing is necessary in SRAM fabrication to preserve the underlying dopant profiles and to allow for less expensive glass substrates in LCD manufacture.
To overcome these limitations regarding poly-Si TFTs, poly-Si1-xGex materials have been employed in the low temperature manufacture of thin film transistors. Such transistors are described in King, Applications of Polycrystalline Silicon-Germanium Thin Films in Metal-Oxide-Semiconductor Technologies, Technical Report No. ICL 94-031 (1994); King et al., IEDM, 91, 567 (1991); and King, IEEE Electron Device Letters, 13, 309 (1992). However, in these thin film transistors, while a poly-Si1-xGex material is employed as the active region, a channel layer of silicon is not interposed between the poly-Si1-xGex alloy material and the gate. As these investigators themselves noted, the performance of such poly-Si1-xGex TFTs was not superior to that of the poly-Si TFTs. Moreover, experiments performed by the present inventors indicated that the interface trap state density as calculated from the measured subthreshold slope is not improved in a poly-Si1-xGex TFT relative to poly-Si TFT, and, in the case of an NMOS poly-Si1-xGex TFT is significantly diminished.
In an attempt to construct a poly-Si1-xGex TFT whose performance would match or exceed that of poly-Si TFTs, an investigation was undertaken to fabricate a superior poly-Si1-xGex TFT. Hypothesizing that a very-thin-film silicon layer interposed between a poly-Si1-xGex alloy material and a gate, where the silicon layer is thick enough to result in a high quality poly-Si/SiO2 interface and yet thin enough to allow the channel region to reside at least in part within the poly-Si1-xGex layer, might result in a superior poly-Si1-xGex TFT, a poly-Si1-xGex TFT having an active region and a gate was constructed, whose active region comprises a poly-Si1-xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1-xGex alloy material and the gate. Such a TFT had not been disclosed in the prior art.
Accordingly, an object of the present invention is to provide a novel high-performance poly-Si1-xGex thin film transistor.
It is another object of the present invention to provide a method of fabricating a high-performance poly-Si1-xGex thin film transistor.
These objects, among others, have been obtained with a thin film transistor having an active region and a gate, whose active region comprises a poly-Si1-xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1-xGex alloy material and the gate. Such objects have also been achieved by means of a method of fabricating a poly-Si1-xGex TFT having an active region and a gate, whose active region comprises a poly-Si1-xGex alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1-xGex alloy material and the gate.
Such poly-Si1-xGex thin film transistors are useful for peripheral logic circuits and pixels in active-matrix liquid crystal displays and for load devices in high density SRAMs.